skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.


Search for: All records

Creators/Authors contains: "Liu, Stephanie E"

Note: When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).
What is a DOI Number?

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

  1. Neuromorphic hardware promises to revolutionize information technology with brain-inspired parallel processing, in-memory computing, and energy-efficient implementation of artificial intelligence and machine learning. In particular, two-dimensional (2D) memtransistors enable gate-tunable non-volatile memory, bio-realistic synaptic phenomena, and atomically thin scaling. However, previously reported 2D memtransistors have not achieved low operating voltages without compromising gate-tunability. Here, we overcome this limitation by demonstrating MoS2 memtransistors with short channel lengths < 400 nm, low operating voltages < 1 V, and high field-effect switching ratios > 10,000 while concurrently achieving strong memristive responses. This functionality is realized by fabricating back-gated memtransistors using highly polycrystalline monolayer MoS2 channels on high-κ Al2O3 dielectric layers. Finite-element simulations confirm enhanced electrostatic modulation near the channel contacts, which reduces operating voltages without compromising memristive or field-effect switching. Overall, this work demonstrates a pathway for reducing the size and power consumption of 2D memtransistors as is required for ultrahigh-density integration. 
    more » « less
  2. The convergence of topology and correlations represents a highly coveted realm in the pursuit of novel quantum states of matter [1, 2]. Introducing electron correlations to a quantum spin Hall (QSH) insulator can lead to the emergence of a fractional topological insulator and other exotic time-reversal-symmetric topological order [3– 10], not possible in quantum Hall and Chern insulator systems. However, the QSH insulator with quantized edge conductance remains rare, let alone that with significant correlations. In this work, we report a novel dual QSH insulator within the intrinsic monolayer crystal of TaIrTe4, arising from the interplay of its single-particle topology and density-tuned electron correlations. At charge neutrality, monolayer TaIrTe4 demonstrates the QSH insulator that aligns with single-particle band structure calculations, manifesting enhanced nonlocal transport and quantized helical edge conductance. Interestingly, upon introducing electrons from charge neutrality, TaIrTe4 only shows metallic behavior in a small range of charge densities but quickly goes into a new insulating state, entirely unexpected based on TaIrTe4’s single-particle band structure. This insulating state could arise from a strong electronic instability near the van Hove singularities (VHS), likely leading to a charge density wave (CDW). Remarkably, within this correlated insulating gap, we observe a resurgence of the QSH state, marked by the revival of nonlocal transport and quantized helical edge conduction. Our observation of helical edge conduction in a CDW gap could bridge spin physics and charge orders. The discovery of a dual QSH insulator introduces a new method for creating topological flat minibands via CDW superlattices, which offer a promising platform for exploring time-reversal-symmetric fractional phases and electromagnetism [3–5, 11, 12]. 
    more » « less
  3. Advances in algorithms and low-power computing hardware imply that machine learning is of potential use in off-grid medical data classification and diagnosis applications such as electrocardiogram interpretation. However, although support vector machine algorithms for electrocardiogram classification show high classification accuracy, hardware implementations for edge applications are impractical due to the complexity and substantial power consumption needed for kernel optimization when using conventional complementary metal–oxide–semiconductor circuits. Here we report reconfigurable mixed-kernel transistors based on dual-gated van der Waals heterojunctions that can generate fully tunable individual and mixed Gaussian and sigmoid functions for analogue support vector machine kernel applications. We show that the heterojunction-generated kernels can be used for arrhythmia detection from electrocardiogram signals with high classification accuracy compared with standard radial basis function kernels. The reconfigurable nature of mixed-kernel heterojunction transistors also allows for personalized detection using Bayesian optimization. A single mixed-kernel heterojunction device can generate the equivalent transfer function of a complementary metal–oxide–semiconductor circuit comprising dozens of transistors and thus provides a low-power approach for support vector machine classification applications. 
    more » « less
  4. Abstract Despite significant progress in solution‐processing of 2D materials, it remains challenging to reliably print high‐performance semiconducting channels that can be efficiently modulated in a field‐effect transistor (FET). Herein, electrochemically exfoliated MoS2nanosheets are inkjet‐printed into ultrathin semiconducting channels, resulting in high on/off current ratios up to 103. The reported printing strategy is reliable and general for thin film channel fabrication even in the presence of the ubiquitous coffee‐ring effect. Statistical modeling analysis on the printed pattern profiles suggests that a spaced parallel printing approach can overcome the coffee‐ring effect during inkjet printing, resulting in uniform 2D flake percolation networks. The uniformity of the printed features allows the MoS2channel to be hundreds of micrometers long, which easily accommodates the typical inkjet printing resolution of tens of micrometers, thereby enabling fully printed FETs. As a proof of concept, FET water sensors are demonstrated using printed MoS2as the FET channel, and printed graphene as the electrodes and the sensing area. After functionalization of the sensing area, the printed water sensor shows a selective response to Pb2+in water down to 2 ppb. This work paves the way for additive nanomanufacturing of FET‐based sensors and related devices using 2D nanomaterials. 
    more » « less
  5. The increasing complexity of deep learning systems has pushed conventional computing technologies to their limits. While the memristor is one of the prevailing technologies for deep learning acceleration, it is only suited for classical learning layers where only two operands, namely weights and inputs, are processed simultaneously. Meanwhile, to improve the computational efficiency of deep learning for emerging applications, a variety of non-traditional layers requiring concurrent processing of many operands are becoming popular. For example, hypernetworks improve their predictive robustness by simultaneously processing weights and inputs against the application context. Two-electrode memristor grids cannot directly map emerging layers’ higher-order multiplicative neural interactions. Addressing this unmet need, we present crossbar processing using dual-gated memtransistors based on two-dimensional semiconductor MoS 2 . Unlike the memristor, the resistance states of memtransistors can be persistently programmed and can be actively controlled by multiple gate electrodes. Thus, the discussed memtransistor crossbar enables several advanced inference architectures beyond a conventional passive crossbar. For example, we show that sneak paths can be effectively suppressed in memtransistor crossbars, whereas they limit size scalability in a passive memristor crossbar. Similarly, exploiting gate terminals to suppress crossbar weights dynamically reduces biasing power by ∼20% in memtransistor crossbars for a fully connected layer of AlexNet. On emerging layers such as hypernetworks, collocating multiple operations within the same crossbar cells reduces operating power by ∼ 15 × on the considered network cases. 
    more » « less